Gate arrays are a type of programmable or semi-custom semiconductor component comprising logic gates having a fixed base pattern, base cells, on an integrated circuit which is programmed or wired by customized metal patterns generally referred to as macros.
In BiCMOS technology (BiCMOS being an acronym standing for bipolar and complementary metal oxide semiconductor), bipolar and complementary metal oxide semiconductor transistors have been formed on the same semiconductor substrate.
BiCMOS gate arrays, until now, have consisted primarily of base cells comprising a CMOS device and a bipolar device in a one-to-one ratio. FIG. 1a is a diagram which illustrates a typical BiCMOS base cell. As shown, a CMOS section lies next to a bipolar section in the cell. FIG. 1b illustrates a more detailed diagram of the CMOS and bipolar sections shown in FIG. 1a. The CMOS section comprises a p-channel and an n-channel device, each denoted by the letter C with the device type, p or n being labeled as such alongside. The bipolar section, as shown in FIG. 1b, includes a bipolar pull-up device, p.u., and a bipolar pull-down device, p.d.. FIG. 1c illustrates a diagram of an alternative base cell to that shown in FIG. 1a. The base cell in FIG. 1c results simply from turning the cell in FIG. 1a on its side. FIG. 1d shows an alternative base cell to that shown in FIG. 1c in which one half of the bipolar section is above the CMOS section and the other half of the bipolar section is below the CMOS section. The efficiency of these and other prior art base cells is poor. Implementation of logic functions using such base cells often result in large amounts of unused bipolar transistors area on the semiconductor substrate in order to fully accommodate the logic function.
A need exists for a BiCMOS gate array which has a base cell that allows increased substrate usage and better efficiency.